1. Description of the Prior Art
A known design of logic-linking circuits using integrated MOS-techniques for binary signal transmission includes the use of static gates and a MOS-transistor connected as a load transistor with at least one switching MOS-transistor connected in series. The point of connection of the load transistor and the switching transistor is the output of the stage, while the control electrode(s) of the switching transistor(s) represent the input of the stage. Whenever the current path, which consists of the switching transistors, is switched, a d.c. signal flows across the entire stage. Therefore, a stage of this kind has considerable rest power losses. In the case of a multi-stage, logic circuit which executes logic or arithmetic operations with resulting carry signals (for example addition of multi-bit words), the power loss becomes very considerable.
Furthermore, to safeguard against interference, a specific minimum signal range must be ensured at the output of such gate stages. This signal range is determined by the conductivity ratio of the switching transistors to the load transistor; the conductivity ratio being determined by the characteristic transistor values: namely, channel length and channel width. Therefore, gates of this kind are also referred to as ratio gates. To assure that the signal range is sufficient, this ratio of channel width to channel length must be selected high for the MOS-transistor which is connected as a load transistor. Consequently, freedom of dimensioning is limited by static ratio gates. This is particularly disadvantageous for the switching times of such gates. If the output resistance is high as a result of the above-mentioned dimensioning regulation regarding the signal range, the time constants consisting of the output resistance of a preceding stage and the capacitive input resistance of the following stage are also high, as a result of which the switching times are of a corresponding length.
In order to avoid the above-mentioned disadvantage in ratio gates, ratio-free dynamic gates have been used. In ratio-free dynamic gates, however, the advantage of low d.c. power losses is accomplished at the cost of greater circuit complexity due to the required control pulse trains.
It is known that MOS-transistors have a symmetrical switching characteristic, i.e., they can be connected by way of their controlled path between source and drain directly into a signal-conducting path such that signal transfer in both directions is possible as a function of control signals connected to the control electrode.
2. Field of the Invention
The field of art to which this invention pertains is a multi-stage logic circuit employing integrated MOS-circuit techniques to produce carry signals.